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 Diffpair gap definition and design synchronization

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cioma Posted - 05 Aug 2016 : 15:38:42
It seems that there is a problem with diffpair gap definition and design synchronization: If layer gaps are defined for a diffpair in the layout Pulsonix considers schematic and layout to be out of sync. And if design synchronization is performed then those diffpair gap definitions are deleted in the layout. Does anyone else experience such behavior.
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cioma Posted - 08 Aug 2016 : 16:01:18
Thanks, Steve, it seems to be working OK.
steve Posted - 08 Aug 2016 : 14:43:40
Thank you for the design files. With the PCB Design Settings switch 'Allow Update of the Schematic to PCB' set on, you can synchronise the rules on the Diff's back to the schematic. On my test they were updated into the schematic and no changes were seen in the PCB.

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steve Posted - 08 Aug 2016 : 11:27:40
Please provide schematic and PCB data to support@pulsonix.com for review

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cioma Posted - 08 Aug 2016 : 10:58:43
Well in my case Synchronise is deleting per layer definitions in the layout. I assume it's not the intended behavior, right?
steve Posted - 08 Aug 2016 : 09:35:44
In schematic the Electronics Engineer can define a set of rules except for individual internal layers, which is why Synchronise will deal with all rules except those.

Behind the scenes, units are system units, the units the user wishes to see for a design are those system units shown in the chosen unit.

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cioma Posted - 05 Aug 2016 : 17:16:18
Well, as I understand diffpair rules in schematic can't have a by layer gap definition as schematic technology file doesn't have layers definitions. Besides in my case units in schematic technology file are mils (1/1000 inch) but in layout technology file units are mm. Perhaps design synchronization logic should ignore those definitions in the layout technology file that are absent in the schematic technology file?
steve Posted - 05 Aug 2016 : 16:50:23
The standard design flow in Pulsonix is that SCM is the design master, although the layout person is allowed to change certain design rules/states, which can be checked on synchronise.

On synchronise, rules in the SCM will dictate over those changed in the PCB on Update, unless the PCB Design Settings switch 'Allow Update of the Schematic to PCB' is set, where Synchronise will offer an Update to the SCM as well. Safe Mode settings may need to change to allow this to happen.

Please refer to Help - Design Settings - General - Synchronise with Schematic.

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