Note: You must be registered in order to post a reply. To register, click here. Registration is FREE!
T O P I C R E V I E W
Posted - 10 Oct 2013 : 14:03:26 A customer suggestion has been received for an option to form a ‘lozenge’ shape clearance around associated differential pair via’s when within copper pour areas of a design. The aim stated, is to improve capacitance readings. This would change the normal resultant ‘figure eight’ clearance form to a lozenge with straight sides, effectively removing the copper ingress towards the centre region between the two associated via’s. The attached graphic example shows this.
We would like to gauge opinion and interest in providing this option, is it an option that you would use within your designs?
2 L A T E S T R E P L I E S (Newest First)
Posted - 10 Oct 2013 : 15:21:59 I have done 5Ghz diff pait stuff, and Steve is correct. You do not want any ground between the two vias. I normally just add extra clearance around the vias and it opens it enough that the result is the same. Xilinx did a really good write up on the subject a few years ago. I did what they suggested and I have not had problems running at 5Ghz. (Of course that is not the only thing you need to do to run at that speed)
Posted - 10 Oct 2013 : 15:09:51 I would be skeptical and want to see the different shown on the client's analyzer of choice. I haven't done enough designs using diff pairs, but I have done some 50ohm RF stuff where I'm just careful and the EE's testing the design have been very happy with the results. (they expected more losses than they saw... and less dB loss makes RF EE's happy. ;) )
Ultimately, if they asked for it -- they should get it.
And if it doesn't work out like they thought -- well, they should get an analyzer and test this stuff before asking for it. ;)