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bkamen
USA
49 Posts |
 Posted - 06 Oct 2016 : 18:31:00
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Hey all (or Pulsonix support),
Is there a doc that describes the best practice method for doing filled and possibly blind vias for pads on a CSP or BGA package?
I have a WLCSP package that uses 0.40mm pitch on 0.20mm pads and the example layouts from the MFR show lovely filled vias. (I'm assuming as well those are probably laser drilled vias. I haven't yet found an example file that specifies the drill table. :( )
Thanks,
-Ben
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ben@benkamen.net
http://www.benjammin.net |
Edited by - bkamen on 07 Oct 2016 20:01:09 |
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steve
United Kingdom
316 Posts |
Posted - 07 Oct 2016 : 08:47:40
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I would advise taking a different approach. The manufacturer of a device like this always recommends nice flat surfaced pads so talk to the board manufacturers direct, obtain knowledge of what they can achieve regarding vias, then decide your design approach. You may well need to consider external layers with laser cut micro-vias.
Pulsonix Assistance |
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jameshead
United Kingdom
125 Posts |
Posted - 07 Oct 2016 : 08:59:45
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Are you after a guide in general or how to do it in Pulsonix?
The HDI Handbook is free from this link http://www.hdihandbook.com/index.php and includes some of the IPC-2226 standard in the text. I've only read sections but you may find useful info in here.
The Advanced Technology option for Pulsonix is very good at handling microvias if you've not already got this.
The PCB fabricator will require a separate gerber file that shows which vias you want capped so you could create a new layer class for this with appropriate layers (layer class "CappedVias", layers "Top Capped Vias" and "Bottom Capped Vias") then use the "By Layer" to set up this layer for the pads for the device.
I would put down a normal round pad in the footprint, then in the design use Alt Pad style to switch individual pads over to the pad style that includes a micro-via and the "by layer" setting to have the same pad style/size on the CappedVia layer.
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bkamen
USA
49 Posts |
Posted - 07 Oct 2016 : 19:12:32
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You've actually both answered the question with information I'll find handy.
Thanks!
-Ben
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ben@benkamen.net
http://www.benjammin.net |
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bkamen
USA
49 Posts |
Posted - 31 Jan 2020 : 07:41:38
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Hey James,
It's funny - i ended up doing that last design using the QFN -- so I never finished setting up the footprint for this.
But now the client is back wanted to super-shrink the design as much as possible which will probably utilize this.
So - to answer your questions followed by maybe 2 more...
Yes, Pulsonix for me has micro-via option available.
So, for the capped-Via (top) and (bottom) - are those electrical layers or a free-form named class?
-Ben
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ben@benkamen.net
http://www.benjammin.net |
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jameshead
United Kingdom
125 Posts |
Posted - 31 Jan 2020 : 09:25:08
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The layer classes I mention to indicate capped status are not Electrical layer classes but Non-Electrical.
Create a layer class called CappedVias
Create layers Capped Vias Top and Capped Vias Bottom of this layer class.
Use the Pad Condition switches to enable Surface Mount and Through Hole and to select the box "Exception Only".
Use the Pad Types switches to enable all the pad types.
In pad styles your device will have its normal pad style. Select this and press the Copy button to create a new pad style, then make sure you can use this pad style for vias and micro-vias and use By Layer to select the Capped Vias Top layer and enter the size of the pad.
In the layout draw a track from the component pad and finish on a via and use the new pad style you created, with the appropriate layer span, then drag that via over the original pad you have a via over the same pad. Ignore any drill in pad DRC errors.
Make sure you output the Capped Via Top layer in a gerber file.
All you are doing is providing the fabricator with a drawing showing the positions of the vias to be capped.
The same process can be used for indicating slots, hard gold selective plating, pin-in-paste through holes etc.
I've written before, either here, or on the old Yahoo Pulsonix user group about this technique for another purpose.
Perhaps if I ever get the time I should create an App Note on this! |
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jameshead
United Kingdom
125 Posts |
Posted - 31 Jan 2020 : 09:29:43
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Example files. Look for pad 99/B3 on IC1.
As a side note, this MSP device has QFN and BGA footprints and using pad names of this type 99/B3 etc. enables you to have the same symbol in the circuit diagram for both packages and be able to change between them without your schematic diagram getting messed up.
PCB file
Download Attachment:  MicroviaExample.pcb
175.54 KB
Schematic File
Download Attachment: MicroviaExample.sch
149.94 KB |
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bkamen
USA
49 Posts |
Posted - 31 Jan 2020 : 10:19:43
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Got the files. Thanks! This really helps.
Yea - I saw the combo-symbol and how you did that. :)
My only question having seen this now is:
Where is the dimensions for the microvia defined?
I see how the pad, if selected, is shown in Technology->Pad but I'm not seeing where the microvia is defined.
-Ben
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ben@benkamen.net
http://www.benjammin.net |
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jameshead
United Kingdom
125 Posts |
Posted - 31 Jan 2020 : 10:26:54
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The microvia used for the via in pad is "v25m35v25h15"
I have entered a pad size of 0.25 (Round Width 0.25 mm / Drill Hole 0.15 mm) through the entire stack.
Size of the microvia depends upon the fabricator's design rules.
If you want a larger stop pad in the layer stack then you use By Layer feature to define this.
You'll probably need to press N for next to jump between the pad in the footprint and the via I've placed over it in the same position. |
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bkamen
USA
49 Posts |
Posted - 31 Jan 2020 : 10:43:07
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Ohhh! I see it now.
ok - thanks!
So it's not 1 pad definition -- it's 2 pads on top of each other. (just to be sure)
Could this be done as a single pad "by layer" (out of curiosity)
(I suppose I could try it)
Thanks again James!
-Ben
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ben@benkamen.net
http://www.benjammin.net |
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jameshead
United Kingdom
125 Posts |
Posted - 31 Jan 2020 : 10:49:51
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Yes it's a separate free via for the microvia and a normal pad in the footprint.
Alternatively you could add the via as a breakout via within the footprint and then enable/disable breakout vias if needed however it may get a little unwieldly.
You could if you really wanted to do the normal footprint pad as the microvia but this would lead to some complexity. You would have to have a normal footprint for the device when you wanted to use it without the pin-in pad microvias, and then have a footprint which had the appropriate pads as microvias and that footprint might be unique to that particular board because layer spans of the micro-vias may be different. I don't think this would be a sensible approach. |
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