Pulsonix User Forum

Technical advice from Pulsonix engineers and the wider community.

Username:
Password:
Save Password
Forgot your Password?

 All Forums
 Help with using Pulsonix
 PCB Design
 Via in Pad
Author Previous Topic Topic Next Topic  

georg.schmidt

Germany
25 Posts

Posted - 25 Mar 2014 :  07:01:42  Show Profile  Reply with Quote
Hi,

sometimes it is necessary to apply vias in pads, e.g. for thermal pads.
Is it possible to apply such vias without getting a "Via in pad"-error in the design rule check?

Regards,
Georg

bkamen

USA
49 Posts

Posted - 25 Mar 2014 :  17:04:03  Show Profile  Reply with Quote
Could you be more specific?

I put via's inside QFN/DFN footprints all the time for excess solder channeling as well as heat dissipation and I don't get those errors.

(They are part of the same NET)

There's also a setting when creating footprints to not generate errors for items inside a footprint. (I'll have to go find it again) which could be part of your problem.

-Ben

-Ben
-------------------------------------------
ben@benkamen.net
http://www.benjammin.net
Go to Top of Page

jameshead

United Kingdom
125 Posts

Posted - 26 Mar 2014 :  08:58:27  Show Profile  Reply with Quote
You will always get a DRC error if you've got the "Via In Pad" check turned on, if the via is on the same net as the pad or not. The "Via In Pad" check is under the "Nets" section and may not be turned on by default.

It's a useful check to make sure that vias aren't too close to SMT pads so as to cause solder theiving during reflow.

As Ben says you can add the vias to the footprint and turn off the DRC checking in a footprint if you don't want to see them, however I wouldn't advise doing this.

It's far better to have them come up as errors occasionally and then lock them to indicate you've seen them and that they are okay.

Alternatively you can draw an area around the thermal pad, name the area "thermalpad" for example, then in Set Up Technology use Match Net Class Pair and set up a rule for Ground to Ground net class within Area "thermalpad" and make the Via to Pad spacing minimum spacing 0.00 but this is far too much hassle I would have thought compared to just locking an error.
Go to Top of Page

steve

United Kingdom
316 Posts

Posted - 26 Mar 2014 :  09:35:23  Show Profile  Reply with Quote
I would suggest that the key to the question is that the copper and vias that you wish to be associated with each other but do not want them to cause DRC errors is simply to assign them each a simple common net name (not the future one in the design, just one you think of) within the footprint. If then in the design you wanted to strap the copper to say GND, the copper and the vias will adopt that signal name.

Pulsonix Assistance
Go to Top of Page
  Previous Topic Topic Next Topic  
Jump To: