PulsonixSim provides a range of different synchronous and asynchronous (ripple) counters as standard. Parts are available for 4, 8, 12 and 16 bit counters as these are the most common requirement. Subcircuits are also available in the Spice models for 20, 24, 28 and 32 bit versions as well, but these have not been implemented as parts. All the counters use an active high reset and have an initial count of zero. Count increments on the rising edge of the clock pulse. Because ripple counters inherently generate illegal states because of device delays, these counters are equipped with internal latches. If an inverted clock signal is applied to the enable input, a de-glitched output becomes available on the falling edge of the clock. A carry output is provided to enable easy expansion of a counter.
Note that the load capacitances specified in the <Spice Parameters> for each synchronous counter are per stage as the inputs are unbuffered to minimise propagation delays. With asynchronous counters this is different because of the internal latches. The reset (Rst) load capacitances are double per stage, so the real load is multiplied by twice the number of stages. The clock load also applies to the enable input, so whilst the clock load is singular, the enable (En) input load is also per stage. This is not normally a problem, but input buffers can be added if required.
Shortcuts
Default Keys: F7
Default Menu: Simulation
Command: Edit Spice Value/Model
How To Add A Counter
There are various ways to add a Counter to a Schematic Design:
- From the Parts Browser, click on the Counter category and choose Counter required. Ensure the Spice Category is selected.
- Use Insert Component and with PulsonixSim selected as the Library to look in, select the Counter required.