This tab allows you to setup various fundamental aspects of the design and how it will use the design data you provide. In particular it defines the naming conventions you will be using, which are important in allowing you to interface between the schematic and PCB, and with other tools you may be using. It is recommended that you set these parameters in the technology files you will be using before you start designing.
Shortcuts
Default Keys: None
Default Menu: Setup
Command: Design Settings
Locating this option
Available from:
Setup menu > Design Settings option > Naming page
Setup menu > Technology option > Design Settings > Naming page
Using the Naming Tab
Force To Upper Case
The names of all entities (except Pin Names, see below) are considered case insensitive by the program. That is, a mixture of upper and lower case letters can be used, and upper and lower case letters are considered the same. So if you have a net called ‘Vcc’ you cannot have a net called ‘VCC’, because the names are considered the same. It is sometimes desirable to have all the letters in names to be of the same case, so that no confusion can result. This is particularly true if you are interfacing with a system which is case sensitive, that is, it would treat ‘Vcc’ and ‘VCC’ as different names . Each of the different name types can be forced to upper case, by checking the appropriate checkbox in this dialog. This only applies to new names which you are entering, so you should ensure the correct settings are made before you begin designing.
Default Net Names
When you add a new net to the design, it is assigned a default name, this can subsequently
be named if you so wish, but this
part of the dialog is concerned with the format of the default names. The default name
consists of an optional stem followed by a number (which are allocated sequentially). The
name stem is specified in the top Name Stem control. The Number Width
control specifies the minimum width of the number, which will be padded to the left with leading
zeroes.
For example, a stem of ‘Net’ and a width of ‘2’ gives net names of the form ‘Net01’.
You can change these values after you have begun designing, but this will result in nets being
renamed, which could be undesirable.
Local Net Names
When designing your schematic, by default, Named Nets are considered global. That is, even when using multiple pages and hierarchy, everywhere a net name is used, it refers to the same net. Items using the same net name are connected to the same net. The Local Net Names section of this dialog controls the creation of these named nets, and how their names are generated. This ensures they are unique when producing netlists, or passed forward to the PCB using the Translate To PCB option.
It is possible to define a named net as local, by using the Default to local names option, which means that only items in the same scope can be connected to that net. The scope being all pages in a block instance, or all pages at the design top level (i.e. not in a block instance).
Names Unique Across Design, when checked, ensures that the named net is only used in one scope. So if block instance ‘B1’ has a named net called ‘Net1’, block instance ‘B2’ could not have any reference to a net called ‘Net1’. When this option is unchecked, it is then possible for ‘B2’ to also have a net called ‘Net1’, but it is not the same net and they are not considered connected. Of course when such a design is used in a PCB application these two nets must have unique names. This is where the other controls on the dialog are used.
Local Name Prefix, Owner - Net Separator and Owner Before Net Name switch, control how unique named nets are presented. To make the named nets unique, the owner name is added to them. The way this is done is configurable. You can choose to have the owner name before or after the named net, and also have a prefix and infix. In the example, if we chose a Local Name Prefix of ’$$’, a Separator of ’-’ with the Owner Before Net Name, the nets would be named ‘$$B1-Net1’ and ‘$$B2-Net1’. For nets which are local to the design top level (not in a block instance), you can define the name of this scope as well.
IMPORTANT: Once you have started a design, you cannot change the Names Unique Across Design setting.
Although a default Local Net ($) will be defaulted as a local net, if the Names unique across the design switch is on then it can be changed into a global net by removing its ‘local’ status. If the Names unique across the design switch is off then it cannot, it will be permanently local to the scope it is in.
Net Pages Attribute
When you display the attribute
This attribute might be combined with a Page Link attribute or added to a Page Link Doc Symbol to full utilise its performance and capabilities.
Page Link Attribute
When you display the attribute
Name Options
Checking the Case Sensitive Pin Names box forces pin names to be case sensitive. That is, ‘A1’ and ‘a1’ would be considered different. This is particularly useful if you will be using large pin arrays, where a leading letter designates the row, and you require more than 26 rows.
Checking the Numeric Gate Names box forces gate modifiers to be numbers instead of letters. For example, you may wish to use the U3/1 notation instead of the usual U3-A notation.
Checking the Fill In Gaps In Number Ranges box forces names for new Components, Blocks, Block Instances, Test Points, Branch Points and Star Points to fill in any gaps between name numbers before adding to the end of the number range. For example, if there are names ‘A1’ and ‘A3’, having this option checked will add ‘A2’ before adding ‘A4’.
Name Ranges
This set of controls allows you to specify the syntax for defining ranges of Component and Net names. If a Component is given a name which is a range then that component represents a set of components which when passed to the PCB application become a number of separate components, each with the same connectivity.
You can also use name ranges when specifying the nets on a bus.
An example string is generated below the dialog controls to show you how the characters you have specified should be used to form a range. The example U1, U[3-6] on the dialog shown above represents 5 components named ‘U1,U3,U4,U5,U6’.
Pin Names
This specifies the separator to be shown between the Component and Pin names when ever the pin name is shown. For example ‘X1.1’
Define Functional Logic Names
This specifies the separator character used when using the Define Functional Logic Names option.
Component Names
This set of controls allows you to specify how you see Component Names in the schematic design. If you are using a component consisting of several gates, then you will probably want each gate to display its name. Display Gate Name, when checked will cause each gate to be named using the component name followed by the given separator and the gate name. For example ‘U1.a’. Display Connector Pin Name, when checked will cause each connector pin to be named using the component name followed by the given separator and the pin name. For example ‘X1-A1’.
Part Names
Use the Display On Each Gate On Page switch to choose whether part names should be displayed on all gates of a part, or just on one of the gates on each page the part is on.
Related Topics
Parts Editor | SCM Technology Files | Net Names | Translate To PCB | Insert Attribute | Insert Attribute | Insert Bus | Hierarchy | General Design Settings