Pulsonix includes additional features to aid the design of Field Programmable Gate Arrays (FPGA) and the increasing large pin counts associated with this type of device. Most of the major FPGA manufacturers provide their own tools for designing the logic and performing the pin assignments necessary with an FPGA. Interface features are provided in Pulsonix that allow the integration of these tools and the information they generate.
FPGA pin assignment data generated by manufacturers’ tools can be imported into a Part in the Pulsonix library. From there, it can be included with the Part into the schematic and propagated forwards to the PCB layout. Changes to the FPGA pin out can be quickly reloaded into Pulsonix reducing the need for error prone manual editing. Reports about pin swaps performed in the Pulsonix PCB will include additional FPGA information to assist with the process of updating the corresponding pin assignments in the FPGA design system.
Multiple FPGA iterations of the same device may be retained as separate Parts in the Pulsonix library.
The FPGA Design Cycle in Pulsonix
The cycle for designing and using FPGA Parts in Pulsonix is straight forward:
- Create the initial FPGA Part
- Mark the Part as an FPGA using the check box on the Parts Editor - Details page.
- Design your FPGA in your chosen FPGA Development system.
- Export a file of the Pin changes from the FPGA development system.
- In the Pulsonix Part Editor, read the changes back using the Import Pin Data option.
- Next, you need to update the Part using Reload from Library or Replace Part depending on how you manage your Parts.
Importing FPGA Pin Data
FPGA pin information is read into a Pulsonix Part using the Import Pin Data option within the Part Editor.
As some FPGA manufacturers provide pin assignments output suitable for loading in to a spreadsheet, an alternative to using the Import Pin Data option is to use the copy and paste facilities in the Part Editor to manually construct the FPGA pin data. If this method is used, is it important to remember to check the FPGA setting on the Part to take advantage of the additional FPGA features provide by Pulsonix.
The Part to Gate pin mappings may be checked by using the Check Pin Mappings option.
FPGA Pin Data Formats Supported
Altera PIN file format
The Altera Quartus II software will automatically generate a PIN file as part of the FPGA design process. The PIN file is an ASCII text file which contains pin assignments and other pin information for an FPGA design.
Importing a Altera PIN file will assign the Pin Name/Usage values from the file to the Logic Name fields of the Pulsonix Part pins by mapping the Location values from the file to the Pulsonix Part pins’ Pin Name fields. All other fields in the PIN file are currently ignored.
Xilinx PAD file format
A PAD file can be generated by the Xilinx ISE software as Part of the FPGA design process. It is an ASCII file containing the I/O pad assignments and other properties.
Importing a Xilinx PAD file will assign the Pin Name values from the file to the Logic Name fields of the Pulsonix Part pins by mapping the Pin Number values from the file to the Pulsonix Part pins’ Pin Name fields. All other fields in the PAD file are currently ignored.
CSV file format
It is also possible to import (and export) Part pin data in CSV format. If the CSV includes the Logic Name field the Part will be set as an FPGA (if not already set).
Other formats
The list of formats supported by Pulsonix is constantly being extended. If you have a format which is not currently supported, please contact our technical support desk to check if the format is under development or now available.
FPGA Pin Names as Pulsonix Logic Names
Once loaded as Logic Name values attached to the pins on a Pulsonix Part, the FPGA pin names can be used as an aid to making the correct connections in the schematic and laying out the PCB.
When you add an FPGA Part to a schematic (or PCB) design, you can choose to display the Logic Name as an attribute alongside the pin. If you prefer, you can choose to show the Logic Name as part of the tooltip information displayed when you hover the cursor over the pin. The Logic Name is also shown in the Properties dialog for the Component pin.
Additional FPGA specific behaviour
A Part that is marked as an FPGA will trigger the following additional FPGA specific behaviour:
Reloading revised Pin Data into a FPGA Part
A second and subsequent import of the FPGA pin data will not simply add the FPGA pin names to the Pulsonix Logic Name fields again in the same manner as the original import. Rather, where possible, it will switch the Pulsonix pin name values, e.g. “A3”, mapped to the Pulsonix symbol pins by comparing the FPGA pin names in the revised pin data file against the previous set of FPGA pin names held in the Logic Name fields of the Pulsonix Part. This means that the logic representation in the schematic symbol can remain constant even though the pin out for the FPGA has changed. Only FPGA pin names that are unique will switched in this way, those that are common to multiple Pulsonix pins will be loaded using the same method as the original import.
Reloading a revised FPGA Part into a design
Pin out modifications loaded into an FPGA Part must be subsequently applied to the schematic into which a component using the Part has be loaded. This can be done using Reload from Library or Replace Part (depending on whether a new version of the Pulsonix Part was created for the revised FPGA). A component that uses an FPGA Part will be recognised as such and treated differently when mapping the pins (and their connected nets) to the revised Part.
Normally a pin that is connected to a net is mapped to the new Part using the Pulsonix pin name. For FPGA Parts, the net pin will be mapped to the new Part using the FPGA pin name, i.e. the Logic Name field on the Pulsonix Part pin, thus if the FPGA pin out has changed on the new Part although the schematic symbol representation remains constant, the net connectivity will change accordingly. For example, if the pin IC1.A3 (Logic Name:IO_L16P_2) is connected to net IOB, after the Reload the pin IC1.A5 (Logic Name:IO_L16P_2) could be connected to net IOB, with the Logic Name IO_L16P remaining the constant factor.
The connectivity changes caused by the FPGA Part Reload/Replace in the schematic will be propagated to the PCB layout as normal by the Synchronise Design command.
It is also necessary to Reload/Replace the FPGA Part in the PCB design so the revised FPGA pin out is reflected on the component pads. However, unlike in the Schematic, the Reload/Replace will map net pins in the normal manner as the connectivity changes have already been applied via Synchronise.
The sequence of Import Pin Data, Part Reload/Replace, and Synchronise may be repeated as many times as there are revisions of the FPGA design.
Additional Pin Swap information for a FPGA Part
During PCB layout some pin swaps may occur. The Pulsonix Back Annotation report shows what pin swaps have been made. For an FPGA Part, this will additionally show the pin Logic Name representing the FPGA pin name as a guide to making the equivalent change in the FPGA design system.
e.g.
Swap Pad IC1.A3 (IO_L16P_2) and IC1.A5 (IO_L39P_3)
Functional Logic Names
When a Part is marked as FPGA on its Part definition within the Library, once used in the Schematic design you then have access to two options: Define Functional Logic Names from the context menu, and Import Functional Logic Names, also on the context menu. These two functions enable you to define the use of the functional logic names based on generic logic names of the Part, and to import a list of functional logic names if generated from the FPGA tool. More detail is available by accessing these help pages.
Related Topics
Part Editor Details Page | Part Editor Pins Page | Part Editor Gates Page | Exporting Pin Data | Importing Pin Data | Reload from Library | Replace Part | Synchronise Design | Define Functional Logic Names | Import Functional Logic Names